| .. | ||
| .git_ | ||
| .vscode | ||
| src | ||
| trace | ||
| .gitignore | ||
| Cache Simulation Report.pdf | ||
| demo.mp4 | ||
| Makefile | ||
| output.txt | ||
| readme.md | ||
| src.7z | ||
Cache Simulator
Cache simulator created for CDA3101 at the University of Florida. Simulates and compares the hitrates and execution times of direct mapped, n-way set associative, and fully associative caches with first in first out (FIFO) and least recently used (LRU) replacement policies.
Prerequisites
- GCC
- GNU Make
Compiling
cdinto the project root directory (ex.cd cache_simulation)- Run
make
Usage
After compiling, run the program from the project root directory like so:
./bin/main
To change the parameters of the simulations, follow this format:
./bin/main [SETS_PER_CACHE] [BLOCKS_PER_SET] [BYTES_PER_BLOCK]
Examples
To run a simulation of a 32 KB cache with 128 sets per cache, 4 blocks per set, and 64 bytes per block, run the following:
./bin/main 128 4 64
The previous command will produce the following output:
Simulation parameters:
SETS_PER_CACHE: 128
BLOCKS_PER_SET: 4
BYTES_PER_BLOCK: 64
Total cache size: 32768 bytes (32 KB)
Simulating fully associative (FIFO) cache...
Fully associative (FIFO) hit rate: 99.18% (time elapsed 1172ms)
Simulating fully associative (LRU) cache...
Fully associative (LRU) hit rate: 99.25% (time elapsed 1232ms)
Simulating direct mapped cache...
Direct mapped hit rate: 98.72% (time elapsed 202ms)
Simulating set associative (FIFO) cache...
Set associative (FIFO) hit rate: 99.14% (time elapsed 450ms)
Simulating set associative (LRU) cache...
Set associative (LRU) hit rate: 99.22% (time elapsed 457ms)